View CS5317-KS_1182088.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 copyright ? cirrus logic, inc. 1997 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cs5317 16-bit, 20 khz oversampling a/d converter features l complete voiceband dsp front-end - 16-bit a/d converter - internal track & hold amplifier - on-chip voltage reference - linear-phase digital filter l on-chip pll for simplified output phase locking in modem applications l 84 db dynamic range l 80 db total harmonic distortion l output word rates up to 20 khz l dsp-compatible serial interface l low power dissipation: 220 mw description the cs5317 is an ideal analog front-end for voiceband signal processing applications such as high-perfor- mance modems, passive sonar, and voice recognition systems. it includes a 16-bit a/d converter with an inter- nal track & hold amplifier, a voltage reference, and a linear-phase digital filter. an on-chip phase-lock loop (pll) circuit simplifies the cs5317's use in applications where the output word rate must be locked to an external sampling signal. the cs5317 uses delta-sigma modulation to achieve 16-bit output word rates up to 20 khz. the delta-sigma technique utilizes oversampling followed by a digital fil- tering and decimation process. the combination of oversampling and digital filtering greatly eases antialias requirements. thus, the cs5317 offers 84 db dynamic range and 80 db thd and signal bandwidths up to 10 khz at a fraction of the cost of hybrid and discrete solutions. the cs5317's advanced cmos construction provides low power consumption of 220 mw and the inherent re- liability of monolithic devices. ordering information see page 20. i 5()%8) 9rowdjh 5hihuhqfh $,1 1& 3//&orfn*hqhudwru &rpsdudwru wk2ughu 'hflpdwlrq )lowhu 6wdwh %xiihuv 9$ 9$ $*1' 9' 9' '*1' 9&2,1 3+'7 567 02'( &/.,1 '2( &/.287 '$7$ '287 mar 95 ds27f4
analog characteristics (t a = t min - t max ; va+, vd+ = 5v 10%; va-, vd- = -5v 10%; clkin = 4.9152 mhz in clkor mode; 1khz input sinewave; with 1.2 k w , .01 m f antialiasing filter.) parameter* min typ max units specified temperature range 0 to 70 c resolution 16 - - bits dynamic performance dynamic rnage (note 1) 78 84 - db total harmonic distortion 72 80 - db signal to intermodulation distorition - 84 - db dc accuracy differential nonlinearity (note2) - 0.4 -lsb positive full-scale error - 150 -mv positive full-scale drift - 500 - m v/c bipolar offset error - 10 -mv bipolar offset drift - 50 - m v/c filter characteristics absolute group delay (note 3) 78.125 - - m s passband frequency (note 4) - 5 - khz input characteristics ac input impedance (1khz) - 80 - k w analog input full scale signal level 2.75 --v power supplies power dissipation (note5) - 220 300 mw notes: 1. measured over the full 0 to 9.6khz band with a -20db input and extrapolated to full-scale. since this includes energy in the stopband above 5khz, additional post-filtering at the cs5317s output can typically achieve 88db dynamic range by improving rejection above 5khz. this can be increased to 90db by bandlimiting the output to 2.5khz. 2. no missing codes is guaranteed by design. 3. group delay is constant with respect to input analog frequency; that is, the digital fir filter has linear phase. group delay is determined by the formula d grp = 384/clkin in clkor mode, or 192/clkout in any mode. 4. the digital filters frequency response scales with the master clock. its -3db point is determined by f -3db = clkin/977.3 in clkor mode, or clkout/488.65 in any mode. 5. all outputs unloaded. all inputs cmos levels. * refer to the parameter definitions section after the pin description section. cs5317 2 ds27f4
analog characteristics (continued) parameter min typ max units power supply rejection va+ (note 6) va- vd+ vd- - - - - 60 45 60 55 - - - - db db db db specified temperature range 0 to 70 c phase-lock loop characteristics vco gain constant, ko (note 7) -4 -10 -30 mrad/vs vco operating frequency 1.28 - 5.12 mhz phase detector gain control, kd -3 -8 -12 m a/rad phase detector prop. delay (note 8) - 50 100 ns notes: 6. with 300mv p-p, 1khz ripple applied to each supply separately. 7. over 1.28 mhz to 5.12 mhz vco output range, where vco frequency = 2 * clkout. 8. delay from an input edge to the phase detector to a response at the phdt output pin. digital characteristics (t a = t min - t max ; va+, vd+ = 5v 10%; va-, vd- = -5v 10%) all measurements performed under static conditions. parameter symbol min typ max units high-level input voltage v ih 2.0 - - v low-level input voltage v il --0.8v high-level output voltage (note 9) v oh (vd+)-1.0v - - v low-level output voltage i out = 1.6ma v ol --0.4v input leakage current i in --10 m a 3-state leakage current i oz -- 10 m a digital output pin capacitance c out -9-pf note: 9. i out =-100 m a. this specification guarantees the ability to drive one ttl load (v oh =2.4v @ i out =-40 m a.). recommended operating conditions (dgnd, agnd = 0v, see note 10.) parameter symbol min typ max units dc power supplies: positive digital negative digital positive analog negative analog vd+ vd- va+ va- 4.5 -4.5 4.5 -4.5 5.0 -5.0 5.0 -5.0 5.5 -5.5 5.5 -5.5 v v v v master clock frequency f clk 0.01 - 5.12 mhz note: 10. all voltages with respect to ground. specifications are subject to change without notice. cs5317 ds27f4 3
switching characteristics (t a = t min -t max ; c l =50 pf; vd+ = 5v 10%; vd- = -5v 10%) parameter symbol min typ max units master clock frequency: clkin clkg1 mode clkg2 mode clkor mode f clkg1 f clkg2 f clkor - - - - - - 20 10 5.12 khz khz mhz output word rate: dout f dout --20khz rise times: any digital input any digital output t risein t riseout - - 20 15 1000 20 ns ns fall times: any digital input any digital output t fallin t fallout - - 20 15 1000 20 ns ns clkin duty cycle clkg1 and cklg2 modes pulse width low pulse width high clkor mode pulse width low pulse width high t pwl1 t pwh1 t pwl1 t pwh1 200 200 45 45 - - - - - - - - ns ns ns ns rst pulse width low t pwr 400 - - ns set up times: rst high to clkin high clkin high to rst high t su1 t su2 40 40 - - - - ns ns propagation delays: doe falling to data valid clkin rising to dout falling (note 11) doe rising to hi-z output clkout rising to dout falling clkout rising to dout rising clkout rising to data valid clkin rising to clkout falling (note 12) clkin rising to clkout rising (note 12) t phl1 t phl2 t plh1 t plh2 t plh3 t plh4 t plh5 t plh6 - - - - - - - - - 1 - - - - - - 150 - 80 60 60 100 200 200 ns clkout cycles ns ns ns ns ns notes: 11. clkin only pertains to clkg1 and clkg2 modes. 12. only valid in clkor mode. absolute maximum ratings (dgnd, agnd = 0v, all voltages with repect to groung) parameter symbol min max units dc power supplies: positive digital negative digital positive analog negative analog vd+ vd- va+ va- -0.3 0.3 -0.3 0.3 (va+) + 0.3 -6.0 6.0 -6.0 v v v v input current, any pin except supplies (note 13) i in - 10 ma analog input voltage (ain and vref pins) v ina (va-) - 0.3 (va+) + 0.3 v digital input voltage v ind -0.3 (vd+) + 0.3 v ambient operating temperature t a -55 125 c storage temperature t stg -65 150 c notes: 13. transient currents up to 100ma will not cause scr latch-up. warning:operating this device at or beyond these extremes may result in permanent damage to the device. normal operation of the part is not guaranteed at these extremes. cs5317 4 ds27f4
2.0 v 0.8 v t fallin t risein 2.4 v 0.4 v t riseout t fallout rise and fall times data clkout (note 15) clkin dout doe clkin t pwh1 t pwl1 clkin clkout (note 14) t plh5 t su1 t su2 t pwr t plh5 t su1 t su2 t plh6 rst dout t plh1 t plh2 t plh3 t phl2 t phl1 14 10 15 (msb) (note 16) t plh4 notes: 14. clkin only pertains to clkg1 and clkg2 modes. 15. if doe is brought high during serial data transfer, clkout, dout, and data will immediately 3-state and the rest of the serial data is lost. 16. rst must be held high except in the clock override (clkor) mode where it can be used to align the phases of all internal clocks. clkin timing serial output timing reset timing cs5317 ds27f4 5
general description the cs5317 functions as a complete data conver- sion subsystem for voiceband signal processing. the a/d converter, sample/hold, voltage refer- ence, and much of the antialiasing filtering are performed on-chip. the cs5317s serial interface offers its 16-bit, 2s complement output in a for- mat which easily interfaces with industry-standard micros and dsps. the cs5317 also includes a phase-locked loop that simplifies the converters application in sys- tems which require sampling to be locked to an external signal source. the cs5317 continuously samples its analog input at a rate set by an exter- nal clock source. on-chip digital filtering, an integral part of the delta-sigma adc, processes the data and updates the 16-bit output register at up to 20 khz. the cs5317 can be read at any rate up to 20 khz. the cs5317 is a cs5316 with an on-chip sam- pling clock generator. as such, it replaces the cs5316 and should be considered for all new de- signs. in addition, a cs5316 look-alike mode is included, allowing a cs5317 to be dropped into a cs5316 socket. theory of operation the cs5317 utilizes the delta-sigma technique of executing low-cost, high-resolution a/d conver- sions. a delta-sigma a/d converter consists of two basic blocks: an analog modulator and a digi- tal filter. conversion the analog modulator consists of a 1-bit a/d converter (that is, a comparator) embedded in an analog negative feedback loop with high open- loop gain. the modulator samples and converts the analog input at a rate well above the band- width of interest (2.5 mhz for the cs5317). the modulators 1-bit output conveys information in the form of duty cycle. the digital filter then processes the 1-bit signal and extracts a high resolution output at a much lower rate (that is, 16-bits at a 20 khz word rate with a 5 khz input bandwidth). an elementary example of a delta-sigma a/d converter is a conventional voltage-to-frequency converter and counter. the vfcs 1-bit output conveys information in the form of frequency (or duty-cycle), which is then filtered (averaged) by the counter for higher resolution. in comparison, the cs5317 uses a more sophisticated multi-order modulator and more powerful fir filtering to ex- tract higher word rates, much lower noise, and more useful system-level filtering. filtering at the system level, the cs5317s digital filter can be modeled exactly like an analog filter with a few minor differences. first, digital filtering re- sides behind the a/d conversion and can thus reject noise injected during the conversion proc- ess (i.e. power supply ripple, voltage reference noise, or noise in the adc itself). analog filtering cannot. also, since digital filtering resides behind the a/d converter, noise riding unfiltered on a near- full-scale input could potentially saturate the adc. in contrast, analog filtering removes the noise before it ever reaches the converter. to ad- dress this issue, the cs5317s analog modulator and digital filter reserve headroom such that the device can process signals with 100mv "excur- sions" above full-scale and still output accurately converted and filtered data. filtered input signals above full-scale still result in an output of all ones. an application note called "delta sigma over- view" contains more details on delta-sigma conversion and digital filtering. cs5317 6 ds27f4
system design with the cs5317 like a tracking adc, the cs5317 continuously samples and converts, always tracking the analog input signal and updating its output register at a 20 khz rate. the device can be read at any rate to create any system-level sampling rate desired up to 20khz. clocking oversampling is a critical function in delta-sigma a/d conversion. although system-level output sample rates typically remain between 7khz and 20khz in voiceband applications, the cs5317 ac- tually samples and converts the analog input at rates up to 2.56 mhz. this internal sampling rate is typically set by a master clock which is on the order of several megahertz. see table1 for a com- plete description of the clock relationships in the various cs5317 operating modes. some systems such as echo-canceling modems, though, require the output sampling rate to be locked to a sampling signal which is 20 khz or below. for this reason the cs5317 includes an on-chip phase-lock loop (pll) which can gener- ate its requisite 5.12 mhz master clock from a 20 khz sampling signal. the cs5317 features two modes of operation which utilize the internal pll. the first, termed clock generation 1 (clkg1), accepts a sam- pling clock up to 20 khz at the clkin pin and internally generates the requisite 5.12 mhz clock. the cs5317 then processes samples updating its output register at the rate defined at clkin, typi- cally 20 khz. for a 20 khz clock input the digital filters 3 db corner is set at 5.239 khz, so clkg1 provides a factor of 2x oversampling at the sys- tem level (20 khz is twice the minimum possible sampling frequency needed to reconstruct a 5 khz input). the clkg1 mode is initiated by ty- ing the mode input to +5v. +5v analog supply 0.1 m f 1 2 10 w cs5317 11 ain signal conditioning 14 4 10 va- agnd dgnd vd- 0.1 15 12 refbuf va+ vd+ 7 9 clock source source signal analog -5v analog supply 6 5 serial data interface 8 3 16 up or dsp control (clock gen. mode / clkg2) vd- (clock override mode / clkor) vd+ (clock gen. mode / clkg1) 17 phdt m f vcoin 18 va+ 10 w 25 nf 25 k w 2.75v 10 m f 10 m f 10 m f 10 m f 0.1 m f clkin mode clkout data doe rst dout 0.1 m f 0.1 m f figure 1. system connection diagram with example pll components cs5317 ds27f4 7
the second pll mode is termed clock genera- tion 2 (clkg2) which generates its 5.12 mhz clock from a 10 khz external sampling signal. again, output samples are available at the system sampling rate set by clkin, typically 10 khz. for the full-rated 10 khz clock clkg2 still sets the filters 3 db point at 5 khz. therefore, clkg2 provides no oversampling beyond the nyquist requirement at the system level (10 khz : 5 khz) and its internal digital filter pro- vides little anti-aliasing value. the clkg2 mode is initiated by grounding the mode pin. the cs5317 features a third operating mode called clock override (clkor). initiated by ty- ing the mode pin to -5v, clkor allows the 5.12 mhz master clock to be driven directly into the clkin pin. the cs5317 then processes sam- ples updating its output register at f clkin /256. since all clocking is generated internally, the clkor mode includes a reset capability which allows the output samples of multiple cs5317s to be synchronized. the cs5317 also has a cs5316 compatible mode, selected by tying rst low, and using mode (pin 7) as the fsync pin. see the cs5316 data sheet for detailed timing informa- tion. analog design considerations dc characteristics the cs5317 was designed for signal processing. its analog modulator uses cmos amplifiers re- sulting in offset and gain errors which drift over temperature. if the cs5317 is being considered for low-frequency (< 10 hz) measurement appli- cations, crystal semiconductor recommends the cs5501, a low-cost, d.c. accurate, delta-sigma adc featuring excellent 60 hz rejection and a system-level calibration capability. the analog input range and coding format the input range of the cs5317 is nominally 3v, with 250 mv possible gain error. because of this gain error, analog input levels should be kept below 2.75v. the converters serial output ap- pears msb-first in 2s complement format. antialiasing considerations in applying the cs5317, aliasing occurs during both the initial sampling of the analog input at f s in (~2.5 mhz) and during the digital decimation process to the 16-bit output sample rate, f s out . mode symbol mode pin reset output word rate provides system-level 2x oversampling clkin (khz) clkout f sin (mhz) dout f sout (khz) f (khz) t dcd * (ns) clock gen. 2 clkg2 clkg2 clkg2 0v high no 7.2 9.6 10.0 (max) 1.8432 2.4576 2.56 7.2 9.6 10.0 14.4 19.2 20.0 542.5 406.9 390.6 clock gen. 1 clkg1 clkg1 clkg1 +5v high yes 14.4 19.2 20.0 (max) 1.8432 2.4576 2.56 14.4 19.2 20.0 14.4 19.2 20.0 542.5 406.9 390.6 clock override clkor clkor clkor -5v sync yes 3686.4 4915.2 5120.0 (max) 1.8432 2.4576 2.56 14.4 19.2 20.0 14.4 19.2 20.0 n/a n/a n/a cs5316 cs5316 fsync low yes 5120.0 (max) 2.56 20.0 20.0 n/a * t dcd - delay from clkin rising to dout falling = 1 clkout cycle table 1. mode comparisons cs5317 8 ds27f4
initial sampling the cs5317 samples the analog input, ain, at one-half the master clock frequency (~2.5 mhz max). the input sampling frequency, f s in , appears at clkout regardless of whether the master clock is generated on-chip (clkg1 and clkg2 modes) or driven directly into the cs5317 (clkor mode). the digital filter then processes the input signal at the input sample rate. like any sampled-data filter, though, the digital filters passband spectrum repeats around integer multiples of the sample rate, f s in . that is, when the cs5317 is operating at its full-rated speed any noise within 5 khz bands around 2.5 mhz, 5 mhz, 7.5 mhz, etc. will pass unfiltered and alias into the baseband. such noise can only be filtered by analog filtering before the signal is sampled . since the signal is heavily oversampled (2.5 mhz : 5 khz, or 500 : 1), a single-pole passive rc filter can be used as shown in figure 2. 0 f 2f 3f dc 5 khz 10 khz 20 khz 40 khz 60 khz .25 f .5 f 0 -40 -80 -2.74 db f ? ? ? ? ? sin ( 128 p| t ) 128sin (p| t ) ? ? 3 ? ? ? = magnitude where: t = 1/ | sin | sin = input sampling frequency = clkout frequency for all modes = clkin/2 in clkor mode = clkin*128 in clkg1 mode = clkin*256 in clkg2 mode f = | sin /128 for all modes | = input frequency | sout = | sin /128 = output data rate for clkor & clkg1 = f | sout = | sin /256 = output data rate for clkg2 = f/2 examples: for | sin = 2.56 mhz at | = 5 khz: magnitude is -2.74 db for | sin = 2.56 mhz at | = 10 khz: magnitude is -11.8 db figure 3. cs5317 low-pass filter response mag ? h(e j w ) ? (db) 1.2 k 0.01 m f ain input signal note: any nonlinearities contributed by this filter will be encoded as distortion by the cs5317. therefore a low distortion, high frequency ca- pacitor such as cog-ceramic is recommended. figure 2. anti-alias filter cs5317 ds27f4 9
decimation aliasing effects due to decimation are identical in the clkor and clkg1 modes. aliasing is dif- ferent in the clkg2 mode due to the difference in output sample rates (10 khz vs. 20 khz) and thus will be discussed separately. aliasing in the clkor and clkg1 modes the delta-sigma modulator output is fed into the digital low-pass filter at the input sampling rate, f s in . the filters frequency response is shown in figure 3. in the process of filtering the digitized signal the filter decimates the sampling rate by 128 (that is, f s out = f s in /128). in its most elemen- tary form, decimation simply involves ignoring - or selectively reading - a fraction of the available samples. in the process of decimation the output of the digital filter is effectively resampled at f s out , the output word rate, which has aliasing implications . residual signals after filtering at multiples of f s out will alias into the baseband. for example, an in- put tone at 28 khz will be attenuated by 39.9 db. if f s out = 20 khz, the residual tone will alias into the baseband and appear at 8 khz in the output spectrum. if the input signal contains a large amount of out- of-band energy, additional analog and/or digital antialias filtering may be required. if digital post- filtering is used to augment the cs5317s rejection above f s out /4 (that is, above 5 khz), the filtering will also reject residual quantization noise from the modulator. this will typically in- crease the converters dynamic range to 88 db. further bandlimiting the digital output to f s out /8 (2.5 khz at full speed) will typically increase dy- namic range to 90 db. aliasing in the clkg2 mode aliasing effects in the clkg2 mode can be mod- eled exactly as those in the clkg1 mode with the output decimated by two (from 20 khz to 10 khz). this is most easily achieved by ignoring every other sample. in the clkg2 mode the ratio of the output sampling rate to the filters -3 db point is two, with no oversampling beyond the demands of the nyquist criterion. without the ability to roll-off substantially before f s out /2, the on-chip digital filters antialiasing value is dimin- ished. the clkg2 mode should therefore be used only when the output data rate must be minimized due to communication and/or storage reasons. in ad- dition, adequate analog filtering must be provided prior to the a/d converter. digital design considerations the cs5317 presents its 16-bit serial output msb-first in 2s complement format. the con- verters serial interface was designed to easily interface to a wide variety of micros and dsps. appendix a offers several hardware interfaces to industry-standard processors. clkout data 131211109876543210 msb (sign bit) lsb 15 14 15 14 f out dout figure 4. data output cs5317 10 ds27f4
data output characteristics & coding format as shown in figure 4, the cs5317 outputs its 16- bit data word in a serial burst. the data appears at the data pin on the rising edge of the same clkout cycle in which dout falls. data changes on the rising edge of clkout, and can be latched on the falling edge. the clkout rate is set by the clkin input (f clkin /2 in the clkor mode; f clkin *128 in the clkg1 mode; and f clkin *256 in the clkg2 mode). dout returns high after the last bit is transmitted. after trans- mitting the sixteen data bits, data will remain high until dout falls again, initiating the next data output cycle. a 3-state capability is available for bus-oriented applications. the 3-state control input is termed data output enable, doe, and is asynchronous with respect to the rest of the cs5317. if doe is taken high at any time, even during a data burst, the data, dout and clkout pins go to a high impedance state. any data which would be output while doe is high is lost. power supplies since the a/d converters output is digitally fil- tered in the cs5317, the device is more forgiving and requires less attention than conventional 16- bit a/d converters to grounding and layout arrangements. still, care must be taken at the de- sign and layout stages to apply the device properly. the cs5317 provides separate analog and digital power supply connections to isolate digital noise from its analog circuitry. each sup- ply pin should be decoupled to its respective ground, agnd or dgnd. decoupling should be accomplished with 0.1 m f ceramic capacitors. if significant low frequency noise is present in the supplies, 10 m f tantalum capacitors are recom- mended in parallel with the 0.1 m f capacitors. the positive digital power supply of the cs5317 must never exceed the positive analog supply by more than a diode drop or the chip could be per- manently damaged. if the two supplies are de- rived from separate sources, care must be taken that the analog supply comes up first at power-up. figure 1 shows a decoupling scheme which al- lows the cs5317 to be powered from a single set of 5v rails. the digital supplies are derived from the analog supplies through 10 w resistors to prevent the analog supply from dropping be- low the digital supply. pll characteristics a phase-locked loop is included on the cs5317 and is used to generate the requisite high fre- quency a/d sampling clock. a functional diagram of the pll is shown in figure 5. the pll consists of a phase detector, a filter, a vco (voltage-controlled oscillator), and a counter/di- vider. the phase detector inputs are clkin ( q 1 ) and a sub-multiple of the vco output signal ( q 2 ). the inputs to the phase detector are positive-edge triggered and therefore the duty cycle of the clkin signal is not significant. with this type of phase detector, the lock range of the pll is equal to the capture range and is independent of the low pass filter. the output of the phase detector is in- put to an external low pass filter. the filter characteristics are used to determine the transient response of the loop. the output voltage from the filter functions as the input control voltage to the vco. the output of the vco is then divided in frequency to provide an input to the phase detec- tor. the clock divider ratio is a function of the pll mode which has been selected. phase detector gain (kd) a properly designed and operating phase-locked loop can be described using steady state linear analysis. once in frequency lock, any phase dif- ference between the two inputs to the phase detector cause a current output from the detector during the phase error. while either the +50 m a or the -50 m a current source may be turned on, the average current flow is: cs5317 ds27f4 11
i out avg = kd (q 1 -q 2 ) ? (- 50 m a 2 p) (q 1 -q 2 ) where q 1 is the phase of in1, q 2 is the phase of in2 and kd is the phase detector gain. the factor 2 p comes from averaging the current over a full clkin cycle. kd is in units of micro-am- peres/radian . vco gain (ko) the output frequency from the vco ranges from 1.28 mhz to 5.12 mhz. the frequency is a func- tion of the control voltage input to the vco. the vco has a negative gain factor, meaning that as the control voltage increases more positively the output frequency decreases. the gain factor units are megaradians per volt per second. this is equivalent to 2 p megahertz per volt. changes in output frequency are given by: dw vco = ko d vco in [ko is typ. -10mrad/vs.] counter/divider ratio the cs5317 pll multiplies the clkin rate by an integer value. to set the multiplication rate, a counter/divider chain is used to divide the vco output frequency to develop a clock whose fre- quency is compared to the clkin frequency in the phase detector. the binary counter/divider ra- tio sets the ratio of the vco frequency to the clkin frequency. as illustrated in figure 5, the vco output is always divided by two to yield the clkout signal which is identical in frequency to the delta-sigma modulator sampling clock. the clkout signal is then further divided by either 128 in the clkg1 mode or by 256 in the clkg2 mode. when the divide by two stage is included, the divider ratio (n) for the pll in the clkg1 mode is effectively 256. in the clkg2 mode the divider ratio (n) is 512. loop transfer function as the phase-locked loop is a closed loop system, an equation can be determined which describes its closed loop response. using the gain factors for the phase detector and the vco, the filter ar- rangement and the counter/divider constant n, analysis will yield the following equation which describes the transfer function of the pll: q 2 q 1 = kokdr n s + kokd nc s 2 + kokdr n s + kokd nc this equation may be rewritten such that its ele- ments correspond with the following phase/frequency detect logic in1 in2 down up clkin 1 2 +5v -5v va+ vco 128 2 2 conversion output rate - same frequency as dout internal sync for digital filter delta-sigma sampling clock clkg1 clkg2 clkor clkor vcoin external rc k d = -8 m a/rad k 0 = -10 mrad/v.s r c 50 m a 50 m a (clkout) phdt c 2 figure 5. pll functional diagram cs5317 12 ds27f4
characteristic form in which the damping factor, z , and the natural frequency, w n , are evident: q 2 q 1 = 2 z w n s + w n 2 s 2 + 2 z w n s + w n 2 both the natural frequency and the damping fac- tor are particularly important in determining the transient response of the phase-locked loop when subjected to a step input of phase or frequency. a family of curves are illustrated in figure 6 that indicate the overshoot and stability of the loop as a function of the damping factor. each response is plotted as a function of the normalized time, w n t. for a given z and lock time, t, the w n required can be determined. alternatively, phase lock con- trol loop bandwidth may be a specified parameter. in some systems it may be desirable to reduce the -3db bandwidth of the pll control loop to re- duce the effects of jitter in the phase of the input clock. the 3 db bandwidth of the pll control loop is defined by the following equation: w 3db = w n ? ````````````````` 2 z 2 + 1 + ? ````````` ` ( 2 z 2 + 1 ) 2 + 1 the equations used to describe the pll and the 3 db bandwidth are valid only if the frequency of clkin is approximately 20 times greater than the 3 db corner frequency of the control loop. filter components using the equations which describe the transfer function of the pll system, the following exter- nal filter component equations can be determined: c = kokd n w n 2 r = 2 z w n n kokd the gain factors (ko, kd) are specified in the analog characteristics table. in the event the sys- tem calls for very low bandwidth, hence a corresponding reduction in loop gain, the phase detector gain factor kd can be reduced. a large series resistor (r1) can be inserted between the output of the detector and the filter. then the 50 m a current sources will saturate to the supplies and yield the following gain factor: kd ? - 5v 2 p r 1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 012345678910 0.1 1 10 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 figure 6a. q 2 unit step response figure 6b. second order pll frequency response w n t. q 2 normalized to q 1 w/w n 20 log( q 2 / q 1 ) z = 0.5 z = 0.6 z = 0.7 z = 0.8 z = 0.9 z = 1.0 z = 1.5 z = 2.0 z = 3.0 z = 10.0 z = 10.0 z = 0.5 z = 0.5 z = 10 cs5317 ds27f4 13
in some applications additional filtering may be useful to eliminate any jitter associated with the discrete current pulses from the phase detector. in this case a capacitor whose value is no more than 0.1 c can be placed across the rc filter net- work (c 2 in figure 5). filter design example the following is a step by step example of how to derive the loop filter components. the cs5317 a/d sampling clock is to be derived from a 9600 hz clock source. the application requires the sig- nal passband of the cs5317 to be 4 khz. the on-chip digital filter of the cs5317 has a 3 db passband of clkout/488.65 (see note 4 in the data sheet specifications tables). the 4 khz pass- band requirement dictates that the sample clock (clkout) of the cs5317 be a minimum of 4000 x 488.65 = 1.954 mhz. this requires the vco to run at 3.908 mhz. the 3.908 mhz rate is 407 times greater than the 9600 hz pll input clock. therefore the cs5317 must be set up in mode clkg2 with n = 512. if the clkg1 mode were used (n = 256), too narrow of a signal band- width through the a/d would result. once the operating mode has been determined from the system requirements, a value for the damping factor must be chosen. figure 6 illus- trates the dynamic aspects of the system with a given damping factor. damping factor is gener- ally chosen to be between 0.5 and 2.0. the choice of 0.5 will result in an overshoot of 30 % to a step response whereas the choice of 2.0 will result in an overshoot of less than 5 %. for example pur- poses, let us use a damping factor of 1.0. so, let us begin with the following variables : ko = - 10 mradians/volt.sec kd = - 8 m a/radian n = 512 z = 1.0 to calculate values for the resistor r and capaci- tor c of the filter, we must first derive a value for w n . using the general rule that the sample clock should be at least 20 times higher frequency than the 3db bandwidth of the pll control loop: clkin 3 20 w 3db where clkin = 9600 hz = 2 p 9600 radians/sec. so: w 3db = 2 p 9600/20 = 3016 radians/sec. knowing w 3db and the damping factor of 1.0, we can calculate the natural frequency, w n , of the control loop: w n = w 3db ? ````````````````` 2 z 2 + 1 + ? ````````` ` ( 2 z 2 + 1 ) 2 + 1 w n = 3016 ? ``````````````````` 2 ( 1 ) 2 + 1 + ? `````````` ` ( 2 ( 1 ) 2 + 1 ) 2 + 1 w n = 1215 1 sec once the natural frequency, w n , is determined, values for r and c for the loop filter can be cal- culated: r = 2 zw n n/kokd r = 2(1)(1215 1/s) 512/(-10mrad/v.s.)(-8 m a/rad) r = 15552 v/a = 15.55 k w . use r = 15 k w . c = kokd/n w n 2 c = (-10 mrad/v.s)(- 8 m a/rad)/512 (1215 1/s) 2 c = 105.8 x 10 -9 a.s/v = 105 nf. use 0.1 m f. the above example assumed typical values for ko and kd. your application may require a worst case analysis which includes the minimum or maximum values. table 2 shows some other ex- ample situations and r and c values. cs5317 14 ds27f4
cs5317 performance the cs5317 features 100% tested dynamic per- formance. the following section is included to illustrate the test method used for the cs5317. fft tests and windowing the cs5317 is tested using fast fourier trans- form (fft) techniques to analyze the converters dynamic performance. a pure sine wave is ap- plied to the cs5317 and a "time record" of 1024 samples is captured and processed. the fft algo- rithm analyzes the spectral content of the digital waveform and distributes its energy among 512 "frequency bins". assuming an ideal sinewave, distribution of energy in bins outside of the fun- damental and dc can only be due to quantization effects and errors in the cs5317. if sampling is not synchronized to the input sine- wave it is highly unlikely that the time record will contain an exact integer number of periods of the input signal. however, the fft assumes that the signal is periodic, and will calculate the spectrum of a signal that appears to have large discontinui- ties, thereby yielding a severely distorted spectrum. to avoid this problem, the time record is multiplied by a window function prior to per- forming the fft. the window function smoothly forces the endpoints of the time record to zero, removing the discontinuities. the effect of the "window" in the frequency domain is to convo- lute the spectrum of the window with that of the actual input. the quality of the window used for harmonic analysis is typically judged by its highest side- lobe level. the blackman-harris window used to test the cs5317 has a maximum side-lobe level of -92 db. figure 7 shows an fft plot of a typical cs5317 with a 1 khz sinewave input generated by an "ul- tra-pure" sine wave generator and the output multiplied by a blackman-harris window. arti- facts of windowing are discarded from the signal-to-noise calculation using the assumption that quantization noise is white. all fft plots in this data sheet were derived by averaging the fft results from ten time records. this filters the spectral variability that can arise from capturing finite time records, without disturbing the total energy outside the fundamental. all harmonics and the -92 db side-lobes from the blackman- harris window are therefore clearly visible in the plots. clkin (hz) mode n clkout (mhz) zw 3db w n r * (k w )c * (nf) 7200 clkg2 512 1.8432 1.0 2262 911 11.6 187 9600 clkg2 512 2.4576 1.0 3016 1215 15.5 106 14400 clkg1 256 1.8432 1.0 4524 1822 11.6 94 19200 clkg1 256 2.4576 1.0 6032 2430 15.5 52 * the values for r and c are as calculated using the described method. component tolerances have not been allowed for. notice that ko and kd can vary over a wide range, so using tight tolerances for r and c is not justified. use the nearest conveniently available value. table 2 example pll loop filter r and c values figure 7. cs5317 dynamic performance signal amplitude relative to full scale dc input frequency 0db -20db -40db -60db -80db -100db -120db 9.6 khz 1 khz sampling rate: 19.2 khz full scale: s/(n+d): 81.39 db + 2.75 v _ cs5317 ds27f4 15
full - scale signal - to - noise - plus - distortion [s/(n+d)] is calculated as the ratio of the rms power of the fundamental to the sum of the rms power of the ffts other frequency bins, which include both noise and distortion. for the cs5317, signal-to-noise-plus-distortion is shown to be better than 81 db for an input frequency range of 0 to 9.6 khz (fs/2). harmonic distortion characteristics of the cs5317 are excellent at 80 db full scale signal to thd (typical), as are intermodulation distortion char- acteristics, shown in figure 8. intermodulation distortion results from the modulation distortion of two or more input frequencies by a non-linear transfer function. dnl test figure 9 shows a plot of the typical differential non-linearity (dnl) of the cs5317. this test is done by taking a large number of conversion re- sults, and counting the occurrences of each code. a perfect a/d converter would have all codes of equal size and therefore equal numbers of occur- rences. in the dnl test, a code with the average number of occurrences is considered ideal and plotted as dnl = 0 lsb. a code with more or less occurrences than average will appear as a dnl of greater than or less than zero. a missing code has zero occurrences, and will appear as a dnl of -1 lsb. the plot below illustrates the typical dnl per- formance of the cs5317, and clearly shows the part easily achieves no missing codes. signal amplitude relative to full scale dc input frequency (hz) s/i.m.d.: 84.7 db 0db -20db -40db -60db -80db -100db -120db 800 1450 9600 figure 9. cs5317 dnl plot figure 8. cs5317 intermodulation distortion 0 65,535 codes 32,768 dnl (lsb) +1 0 -1 +1/2 -1/2 schematic & layout review service confirm optimum schematic & layout before building your board. confirm optimum schematic & layout before building your board. for our free review service call applications engineering. for our free review service call applications engineering. call: (512) 445-7222 cs5317 16 ds27f4
pin descriptions (pin numbers refer to the 18-pin dip package) 18 pin dip pinout 20 pin soic pinout power supplies vd+ - positive digital power, pin 2. positive digital supply voltage. nominally 5 volts. vd- - negative digital power, pin 10. negative digital supply voltage. nominally -5 volts. dgnd - digital ground, pin 4. digital ground reference. va+ - positive analog power, pin 1. positive analog supply voltage. nominally 5 volts. va- - negative analog power, pin 14. negative analog supply voltage. nominally -5 volts. agnd - analog ground, pin 15. analog ground reference. pll/clock generator clkin - clock input, pin 9. clock input for both clock generation modes and the clock override mode (see mode). 18 17 1 2 3 4 5 6 7 8 11 10 9 16 15 14 13 12 positive analog power va+ vcoin vco input positive digital power vd+ phdt phase detect data output enable doe rst reset digital ground dgnd agnd analog ground serial clock output clkout va- negative analog power serial data output data nc no connect clocking mode select mode refbuf positive reference buffer data output ready dout ain analog input clock input clkin vd- negative digital power 1 2 3 4 5 6 7 8 10 9 18 17 11 16 15 14 13 12 19 20 positive analog power va+ vcoin vco input positive digital power vd+ phdt phase detect data output enable doe rst reset digital ground dgnd agnd analog ground no connect nc nc no connect serial clock output clkout nc no connect serial data output data va- negative analog power clocking mode select mode refbuf positive reference buffer data output ready dout ain analog input clock input clkin vd- negative digital power cs5317 ds27f4 17
mode - mode set, pin 7. determines the internal clocking mode utilized by the cs5317. connect to +5v to select clkg1 mode. connect to dgnd to select clkg2 mode. connect to -5v to select clkor mode. this pin becomes equivalent to fsync in the csz5316 compatible mode. vcoin - vco input, pin 18. this pin is typically connected to phdt. a capacitor and resistor in series connected between va+ and this pin sets the filter response of the on-chip phase locked loop. phdt - phase detect, pin 17. this pin is typically connected to vcoin. a capacitor and resistor in series connected between va+ and this pin sets the filter response of the on-chip phase locked loop. inputs ain - analog input, pin 11. doe - data output enable, pin 3. three-state control for serial output interface. when low, data, dout, and clkout are active. when high, they are in a high impedance state. rst - sample clock reset, pin 16. sets phase of clkout. functions only in the clock override mode, clkor. used to synchronize the output samples of multiple cs5317s. must be kept high in clkg1 or clkg2 modes. also, tying this pin low, with mode not tied to - 5v, will place the cs5317 into csz5316 compatible mode. outputs dout - data output flag, pin 8. the falling edge indicates the start of serial data output on the data pin. the rising edge indicates the end of serial data output. data - data output, pin 6. serial data output pin. converted data is clocked out on this pin by the rising edge of clkout. data is sent msb first in twos complement format. clkout - data output clock, pin 5. serial data output clock. data is clocked out on the rising edge of this pin. the falling edge should be used to latch data. since clkout is a free running clock, dout can be used to indicate valid data. refbuf - positive voltage reference noise buffer, pin 12. used to attenuate noise on the internal positive voltage reference. must be connected to the analog ground through a 0.1 m f ceramic capacitor. cs5317 18 ds27f4
parameter definitions resolution - the number of different output codes possible. expressed as n, where 2 n is the number of available output codes. dynamic range - the ratio of the largest allowable input signal to the noise floor. total harmonic distortion - the ratio of the rms sum of all harmonics to the rms value of the largest allowable input signal. units in dbs. signal to intermodulation distortion - the ratio of the rms sum of two input signals to the rms sum of all discernible intermodulation and harmonic distortion products. linearity error - the deviation of a code from a straight line passing through the endpoints of the transfer function after zero- and full-scale errors have been accounted for. "zero-scale" is a point 1/2 lsb below the first code transition and "full-scale" is a point 1/2 lsb beyond the code transition to all ones. the deviation is measured from the middle of each particular code. units in %fs. differential nonlinearity - the deviation of a codes width from the ideal width. units in lsbs. positive full scale error - the deviation of the last code transition from the ideal, (vref - 3/2 lsb). units in mv. positive full scale drift - the drift in effective, positive, full-scale input voltage with temperature. negative full scale error - the deviation of the first code transition from the ideal, (-vref + 1/2 lsb). units in mv. negative full scale drift - the drift in effective, negative, full-scale input voltage with temperature. bipolar offset - the deviation of the mid-scale transition from the ideal. the ideal is defined as the middle transition lying on a straight line between actual positive full-scale and actual negative full-scale. bipolar offset drift - the drift in the bipolar offset error with temperature. absolute group delay - the delay through the filter section of the part. passband frequency - the upper -3 db frequency of the cs5317. cs5317 ds27f4 19
ordering guide model number temperature range package cs5317-kp 0 to 70 c 18 pin plastic dip CS5317-KS 0 to 70 c 20 pin plastic soic cs5317 20 ds27f4
appendix a applications figure a1 shows one method of converting the serial output of the cs5317 into 16-bit, parallel words. the associated timing is also shown. s2 a s1 p a p b p c p d p e p f p g p h d0 d1 d2 d3 d4 d5 d6 d7 74hct299 q h p a p b p c p d p e p f p g p h d8 d9 d10 d11 d12 d13 d14 d15 74hct299 cs5317 data dout clkout cs 8 8 16 data bus +5v oe2 +5v oe2 s2 a s1 oe1 oe1 int int only needed for level sensitive interrupt driven systems. d q q set 74hct74 15 13 14 0 2 1 int cleared when data read (cs goes low) (msb) data int clkout dout figure a1. cs5317-to-parallel data bus interface cs5317 ds27f4 21
figure a2 shows the interconnection and timing details for connecting a cs5317 to a nec m pd7730 dsp chip. figure a3 shows the interconnection and timing details for connecting a cs5317 to a motorola dsp 56000. status register (sr) meaning external clock 16 bit data msb first setting 0 1, 0 0 bit 9 7, 6 3 mnemonic sci sdli sif m pd77230 sick si sien cs5317 data clkout dout 15 13 14 data clkout dout 0 2 1 (msb) figure a2. cs5317-to-nec m pd77230 serial interface cs5317 data clkout dout dsp56000 sck, sc0 srd sc2, sc1 ssi control reg. a cra (x:ffec) wl1 = 1 wl0 = 0 16 bits async sc0 sc1 - 0 - 0 0 0 0 sync sck sc2 0 1 - 0 0 0 - clkout dout gck syn fsl sckd scd2 scd1 scd0 pins ssi control reg. b crb (x:ffed) 15 13 14 data clkout dout 0 2 1 (msb) figure a3. cs5317-to-motorola dsp56000 serial interface cs5317 22 ds27f4
figure a4 shows the interconnection and timing details for connecting a cs5317 to a we dsp16 dsp chip. figure a5 shows the interconnection and timing details for connecting a cs5317 with tms32020 and tms320c25 dsp chips. cs5317 data clkout dout dsp16 ick di ild q d 74 data d serial i/o control register (sioc) meaning msb input first ild is an input ick is an input 16 bit input data value 1 0 0 0 field msb ild ick ilen clkout dout data d 15 13 14 2 1 0 (msb) figure a4. cs5317-to-we dsp16 serial interface tms32020 tms320c25 clkr dr fsr cs5317 data clkout dout tms32020 status register (st1): f0 = 0 (16 bit data) tms320c25 status register (st1): fsm = 1 (frame sync used) f0 = 0 (16 bit data) 15 13 14 data clkout dout 0 2 1 (msb) figure a5. cs5317-to-tms32020/tms320c25 serial interface cs5317 ds27f4 23
? notes ?
25 copyright ? cirrus logic, inc. 1998 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cdb5317 evaluation board for cs5317 features l easy to use digital interface parallel 16 bits with clock serial output with clock l multiple operating modes including two pll modes l idc header used to access parallel data, serial data, and clock input and output description the cdb5317 evaluation board is designed to allow the user to quickly evaluate performance of the cs5317 del- ta-sigma analog-to-digital converter. all that is required to use this board is an external power supply, a signal source, a clock source, and an ability to read either serial or parallel 16bitdata words. ordering information cdb5317 evaluation board i clkin cs5317 converter serial to parallel clkout data d0-d15 idc header ain dack +5v -5v gnd clkin drdy v l mar 95 ds27db3
general description the cdb5317 evaluation board is a stand-alone environment for easy lab evaluation of the cs5317 delta-sigma analog-to-digital converter. included on the board is a serial-to-parallel con- verter. the user can access output data in either parallel or serial form. when supplied with the necessary +5 v and -5 v power supplies, a clkin signal, and an analog signal source, the cdb5317 will provide converted data at the 40 pin header. suggested evaluation method an efficient evaluation of the cs5317 using the cdb5317 may be accomplished as described be- low. the following equipment will be required for the evaluation: the cdb5317 evaluation board. a power supply capable of supplying +5v and -5v. a clock source as the clkin signal of the cs5317. a spectrally pure sine wave generator such as the krohn-hite model 4400a "ultra-low distor- tion oscillator". a pc equipped with a digital data acquisition board such as the metrabyte model pio12 "24 bit parallel digital i/o interface". a software routine to collect the data and per- form a fast fourier transform (fft). the evaluation board includes filter components for the on-chip phase locked loop. the compo- nents are adequate for testing if the clkin signal has little or no phase-jitter. if the cdb5317 board is being tested as part of a system which generates a clkin which contains jitter, the pll filter components may need to be optimized for your system (see the cs5317 data sheet). set-up for evaluation is straightforward. first de- cide the operating mode and place the jumper on the board for the proper selection. then decide whether the filter components for the phase locked loop are adequate or whether they should be changed for your evaluation. the pll will lock on a steady clock input with the filter as it is. connect the necessary 5 v (cmos compatible) clkin signal for the application. use the sine- wave generator to supply the analog signal to the cdb5317. apply the analog input and clkin signals only when the evaluation board is pow- ered up. converted data will then appear at the header on the cdb5317. the header should be connected to the digital data acquisition board in the pc through an idc 40 pin connector and ca- ble. the software routine should collect the data from the cdb5317 and run a standard 1024 point fast fourier transform (fft). such an analysis results in a plot similar to figure 1. this plot re- sulted from using a 1khz input signal and a blackman-harris window for the fft. the signal to noise and signal to total harmonic distortion characteristics of the cs5317 may be easily measured in this way. the signal to total harmonic distortion value for a particular input is the ratio of the rms value of the input signal and the sum of the rms values of the harmonics shown in the diagram. the dynamic range of the cs5317 can be measured by reducing the input figure 1. fft plot example signal amplitude relative to full scale dc input frequency 0db -20db -40db -60db -80db -100db -120db 9.6 khz 1 khz sampling rate: 19.2 khz full scale: s/(n+d): 81.39 db 2.75 v cdb5317 26 ds27db3
amplitude so that distortion products become neg- ligible. this allows an accurate measurement of the noise floor. more complex analysis such as intermodulation distortion measurements can be accomplished with the addition of another sine-wave generator. circuit description figure 2 illustrates the cs5317 a/d converter ic circuit connections. the chip operates off of 5v. these voltages are supplied from a power source external to the evaluation board. binding posts are supplied on the board to connect the +5, -5, and ground power lines. a good quality low rip- ple, low noise supply will give the best performance. the +5 v supply can also be used for vl and should be connected between the vl board jack and the power supply, as opposed to connecting the vl jack straight to the +5v jack. the +5v jack is the positive power source for the cs5317 ic whereas the vl jack supplies power to all the digital ics. care should be taken that noise is not coupled between vl and +5v; how- ever, supply noise is generally not a problem with the cs5317 since the on-chip decimation filter will remove any interference outside of its pass- band. the +5 and -5 v supply lines are filtered on u6 9 11 clkin gnd -5v ain tp10 17 18 r11 15 12 r8 10 c13 c12 clkg1 clkg2 clkor clkin (fig.6) p2 10 m f tp9 c18 c16 10 m f d2 6.8v tp7 + tp8 r1* r2 200 51 10k cs5317 +5v d3 c19 c17 r10 6.8v 0.22 m f r7 10 va+ 1 vd+ 2 c7 0.1 m f c6 10 m f r5 10 k clkout data dout (fig. 3) (fig. 3) (fig. 3) r9 10 k r6 10 k 7 16 4 3 5 6 8 0.1 m f c15 0.1 m f 0.1 m f c14 tp6 d1 c4 c5 0.1 m f v l v l 10 m f va- 14 vd- 10 c8 0.1 m f c9 10 m f * remove for logic gate clkin source dgnd clkout data mode rst doe dout ain clkin agnd refbuf phdt vcoin + 1.2k 0.01 m f npo figure 2. analog-to-digital converter cdb5317 ds27db3 27
the board and then connected to the v a + and v a - supply pins of the chip. the +5 v and -5v are then connected by means of ten w resistors to the v d + and v d - pins respectively. capacitive filter- ing is provided on all supply pins of the chip. in addition there is a 0.1 m f filter capacitor con- nected from the refbuf pin of the chip to the v a - supply pin. to properly operate, the cs5317 chip requires an external (5 v cmos compatible) clock. a bnc connector labeled clkin is provided to connect the off-board clock signal to the board. the clkin signal is also available on the 40 pin header connector. the clkin signal is one input to the phase detector of the on-chip phase locked loop of the cs5317. header connector p2 (see figure 2) is provided to allow mode selection for the cs5317 chip. the mode selection works together with the clkin signal to set the sample rate and the output word rate of the cs5317. see the cs5317 data sheet for details on mode selection. two of the avail- able modes (clkg1 and clkg2) utilize the on-chip phase locked loop to step up the clkin frequency to obtain the necessary sample rate clock for the a/d converter. another mode (the clkor mode) does not use the on-chip pll but instead drives the sample function directly. the 1 3 9 11 13 2 4 8 10 12 u5 unused gates d s 2 gnd r 74hc74 cl v l 14 4 c10 0.1 m f d c11 v l r4 10k 0.1 m f 6 u5 5 5 6 q q 14 c1 0.1 m f v l 3 1 13 12 2 7 v l (fig. 2) dout 7 3 5 6 u1 4 clkout (fig. 2) 11 10 9 8 drdy dack (fig. 6) (fig. 6) (fig. 6) dout2 (fig. 6) clkout (fig. 6) clkout2 data data 1 (fig. 6) (fig. 6) data (fig. 2) tp3 tp2 u4 14 7 d 8 10 vl vl q 12 r u4 cl vl 11 vl q 9 s 13 figure 3. buffers and parallel handshake flip-flop cdb5317 28 ds27db3
two modes which use the phase locked loop will require appropriate low pass filter components on the evaluation board. the low pass filter compo- nents help determine the pll control loop response, including its bandwidth and stability and therefore directly affect the transient response of the pll control loop. appropriate filter compo- nents should be installed if a particular dynamic response to changes of the clkin signal is de- sired. the filter components which are installed on the board have been chosen for the following parame- ters: mode: clkg2; clkin: 7,200; n=512; damping factor: 1.0; control loop -3 db band- width: 2262 radians/second. these parameters yield r as 10 k w and c as 0.22 m f for the filter components. the analog signal to be digitized is input to the ain bnc connector. the digital output words from the cs5317 are buffered by hex inverters as shown in figure 3. the buffered versions of the clkout and data signals are available on the header connector p1 in figure 6. the serial data signals out of the cs5317 are illustrated in figure 4. if remote control of the doe line is desired, the trace on the pc board can be opened and a wire connection can be soldered to the doe input line. remote control of the rst line of the cs5317 is also available if desired. figures 5 and 6 illustrate the serial to parallel shift registers including timing information. the data output signal from the cs5317 is input to the data input of the shift register. an inverted version of the clkout signal is used to clock the data into the shift registers. the two 8-bit shift register ics also include output latches. the rising edge note: for a complete description of serial timing see the cs5317 data sheet clkout data 1514131211109876543210 dout figure 4 serial data timing data serial data shifting out parallel data (d0-d15) valid parallel data valid drdy dack dout serial data shifting out figure 5. parallel data timing cdb5317 ds27db3 29
of the dout signal from the cs5317 is used to latch the data once it is input to the shift registers. the rising edge of dout is also used to toggle the drdy flip flop (see figure 3). the flip flop is used to signal a remote device whenever new data is latched into the output registers. the drdy flip flop is reset whenever dack occurs. a component layout of the cdb5317 board is il- lustrated in figure 7. 13 13 u2 d8 d9 d10 d11 d12 d13 d14 d15 data clkout 7 6 5 4 3 2 1 15 qh qg qf qe qd qc qb qa gnd 12 11 14 latch clk shift clk din 74hc595 rst clkin p1 dack d0 d1 d2 d3 d4 d5 d6 d7 drdy 7 6 5 4 3 2 1 15 qh qg qf qe qd qc qb qa u3 gnd 12 11 14 74hc595 8 9 tp4 tp5 10k v l 10 16 0.1 m f c3 v l 10 16 0.1 m f c2 clkout2 (fig. 3) (fig. 2) clkin rst latch clk shift clk din dout data1 (fig. 3) (fig. 2) data (fig. 3) (fig. 3) dout2 clkout drdy (fig. 3) (fig. 3) dack oe 8 r3 figure 6. cdb5317 30 ds27db3
figure 7. bird?s eye view cdb5317 ds27db3 31

▲Up To Search▲

Price & Availability of CS5317-KS

	To Download CS5317-KS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .